This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-251788, filed on Aug. 29, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including a memory cell array in which memory cell strings each constituted of a plurality of memory cells connected in series are aligned in an array form, a nonvolatile semiconductor memory device-integrated system, and a defective block detecting method.
2. Description of the Related Art
Recently, the capacity of nonvolatile semiconductor memory devices is acceleratingly increased. As the one representing a nonvolatile semiconductor memory device, there is a NAND cell type EEPROM (hereinafter, referred to as a flash memory) capable of electrically rewriting data and suitable for high-density design. Each memory cell of the flash memory has a structure in which a floating gate (charge storage layer) and a control gate are formed above a semiconductor substrate via an insulating film. A plurality of memory cells are connected in series so as to share a source and drain to constitute a memory cell string, which is connected to a bit line as a unit. Such memory cell strings are aligned in an array form to constitute a memory cell array.
The drain being one end of the memory cell string is connected to the bit line via a first select gate, and the source being the other end is connected to a common source line via a second select gate. The control gate of each memory cell is continuously connected to each other in a row direction by a word line. Usually, a collective unit of the memory cells connected to the same word line is called a page, a collective unit of the pages sandwiched between a set of the first select gate and second select gate is called a block or a sector (hereinafter, referred to as the block). A collective unit of the blocks connected to the same bit line is called a bank. Switching of the banks is usually performed at the most significant bit of a block address (in the case with the two banks).
In a storage region of the flash memory, the collectively erasable minimum unit is one block. These blocks are given addresses. A page buffer connected to the first select gate via the bit line reads one page of data from the memory cells connected to the same word line WL (it can be also said that the data is transferred to the page buffer from the memory cell), and latches it.
The flash memory is usually guaranteed for all the blocks at the shipment. However, depending on the use, all the blocks do not necessarily need to be non-defectives. This is the same as the cases of hard discs and flexible discs. For this reason, devices such as a NAND type flash memory, for which defective in the blocks of a certain percentage (hereinafter, referred to as defective blocks) is admitted from the beginning to reduce production cost of the flash memory and provide them at a reasonable price, are coming along. The tendency is especially growing more and more as a result of the recent increase in the capacity.
In the case of a flash memory-integrated system (nonvolatile semiconductor memory device-integrated system), which is the system integrated with these devices, an address table that is the address list of the defective blocks is created in the flash memory-integrated system. According to this, the flash memory-integrated system performs a control not to access the defective blocks based on the address table. As for a method of creating the address table, the address table is created by storing flag data in a region of the flash memory where the defective blocks exist by a manufacturer at the shipment, and by detecting and determining it in the flash memory integrated-system.
Here, a method of detecting a defective block of a conventional flash memory-integrated system will be explained with use of the drawing.
FIG. 18 is a flow chart showing a process of detecting a defective block of the conventional flash memory integrated-system. The conventional detecting method includes the steps of inputting an address (step S101), determining a page according to the inputted address (step S102), and transferring data to a page buffer from one page of memory cells (step S103), as shown in FIG. 18.
Next, it is determined whether all bits (that means all output bus of 16 bits) of data read out in sequence by one column from the page buffer are xe2x80x9c1xe2x80x9d (steps S104 to S106). When all the bits of the read data are xe2x80x9c1xe2x80x9d (Yes in step S106), it is determined whether a number M of the columns is the maximum value. If it is the maximum value, the control is transferred to the next step, and if it is not the maximum value, the number of the columns is incremented (step S109), and the control is returned to step S104. When all the bits of the read data are not xe2x80x9c1xe2x80x9d (No in step S106), the inputted address is stored as a block address of the defective block (step S107). When the number M of the columns becomes the maximum value (Yes in step S108), it is determined whether a number N of the pages is the maximum value. If the number N of the pages is the maximum value, the detection process is finished. If the number N of the pages is not the maximum value, the number N of the pages is incremented and the control is returned to step S102.
As explained above, in the conventional detection method, it is necessary to read the data of all the memory cells to an outside and create the address table while confirming presence and absence of the flag data, and the detecting time is increased following the increase in the number of memory cells. For example, in the case of an existing 64M bit NAND type flash memory, the number of pages is 16xc3x971024, and the number of data per page is 528 Bytes. The time taken to transfer the data to the page buffer from the memory cell (the aforementioned step S103) is 7 us per page, a serial access cycle is 20 MHz (50 ns/Byte), and therefore the minimum time required for creating the address table in the flash memory-integrated system is
(7+0.05xc3x97528)xc3x9716xc3x971024=547225.6 us≈550 ms.
There exists the request for reducing the time required for creating the address table described above. Namely, there arises the request for reducing the time taken to detect defective blocks. It is expected that the aforementioned request will increase still further following the increase in capacity in the future.
The present invention is made in consideration of the aforementioned circumstances, and has its object to provide a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device-integrated system, and a defective block detecting method, which are capable of reducing the time required for creating an address table of defective blocks and for detecting the defective blocks.
The present invention is made to solve the aforementioned problem, and is characterized in that in the nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device-integrated system and a defective block detecting method according to the present invention, a block to be a target of detection of flag data is determined, logical product outputting circuit outputs logical product of the data stored in memory cells of each memory cell strings in the determined block, and detection of the flag data is performed for each block based on the output of the logical product outputting circuit, for the nonvolatile semiconductor memory device storing the flag data indicating the defective block in part of the memory cells of the defective block.
As a result, in the nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device-integrated system and the defective block detecting method according to the present invention, the data of all the memory cells in one block is read by onetime processing according to the logical product of each of the memory cell strings, and collective detection of the flag data is performed based on the output of the logical product of each of all the memory cell strings, thus making it possible to detect whether all the memory cells in the selected block have the same data (all bits xe2x80x9c1xe2x80x9d) or not. Namely, it is possible to detect whether different data (xe2x80x9c0xe2x80x9d=flag data indicating a defective block) exists in the selected block or not at a high speed.